[SoC Modelling] Intro

A System on Chip (SoC) integrates hardware and software to communicate with the outside world through various interfaces. The Electronic System Level (ESL) model of an SoC can simulate the entire system’s behavior, executing all the software that will run on the actual SoC with minimal modifications. An alternative name for an ESL model is a Virtual Platform. In some SoC design flows, creating an ESL model is the first design step. During a gradual refinement process, high-level components are progressively replaced with lower-level models or actual implementations. Ultimately, the entire system is implemented, but a robust ESL methodology allows for arbitrary combinations of interacting high-level and low-level modeling styles. A common use case involves having most of the design at a high level while requiring more detailed modeling for one or two subsystems to address specific design issues of current interest.

The terms “high-level” and “low-level” refer to the abstraction levels in modeling:

• High-Level: High-level models are designed with a high level of abstraction, allowing for a simplified and faster simulation of the system’s behavior. These models are primarily used in the early design stages to understand the overall system or evaluate various architecture options. Detailed hardware implementation and cycle-accuracy are often omitted or simplified, making them useful for quickly verifying software and system behavior. For example, SystemC’s Transaction Level Modeling (TLM) is a high-level methodology that models data flow and functional behavior abstractly.
• Low-Level: Low-level models have a lower level of abstraction and simulate the hardware in great detail. These models are mainly used in the later stages of design and operate similarly to the actual hardware implementation. They simulate exact behavior at the clock cycle level and provide detailed insights into how each hardware component functions. Register Transfer Level (RTL) modeling is a typical low-level modeling technique.

This section introduces the main goals and approaches of ESL modeling. It reviews the SystemC modeling library and its transaction library (SystemC TLM), and discusses how high-level models can be calibrated to provide valuable insights into performance and power.

The performance of ESL models should be sufficient to run large programs within a reasonable timeframe, typically achieving at least 1% of the actual system’s performance. ESL models are generally accurate regarding memory layout and content, but many other hardware details are ignored unless specifically critical for testing. This is a key means of achieving high simulation performance.

Fundamentally, ESL models simulate the system starting from a power-on or reset point. Another approach to applying ESL models to complex software involves using checkpoints and replays. This is useful when a significant amount of software needs to run before reaching the point of interest. Checkpoints are chosen at points such as after booting or starting the operating system. At this checkpoint, the complete state of the model is saved to a checkpoint file. While it’s theoretically possible to capture information from a real system, the ESL model may differ from the real system, leading to minor discrepancies. Moreover, instrumenting a real system is challenging, especially if it doesn’t yet exist. Since checkpoints serve as the basis for multiple experiments, the time invested in creating them is compensated.

To perform experiments, the ESL model is loaded with checkpoint data, and modeling proceeds from that point. It is possible to switch to a higher level of detail than was used when preparing the checkpoint, applying this switch to the entire system or only to specific subsystems. For example, a high-level model of an I/O block could be switched to an RTL model.

The following sequence outlines the description of ESL:

1. ESL Modelling of Power, Performance, and Area
2. Interconnect Modelling
3. SystemC Modelling Library
4. Transaction-level Modelling
5. Processor Modelling with Different Levels of Abstraction
6. ESL Modelling of Power, Performance and Area