[ESL Modelling] Interconnect Modelling

Interconnect modeling plays a crucial role in the early stages of SoC design, providing performance analysis and optimization before the actual interconnect is designed. These models also aid in predicting realistic latency when modeling the entire SoC at the Electronic System Level (ESL). Detailed interconnect models can replicate issues encountered in the production phase and serve as a basis for research to resolve them.

Key Concepts in Interconnect Modeling

Both Packetised Networks on Chip (NoC) and traditional Circuit-Switched interconnects handle discrete events involving queuing and arbitration. Due to this similarity, the same modeling techniques can be applied to both systems.

Types of Interconnect Modeling

Interconnect modeling can range from highly abstract to very detailed levels:

1. High-Level Static Analysis: This approach models traffic flow using simple spreadsheets or similar tools with traffic flow matrices. It is suitable for early design stages and can add basic latency estimations to TLM (Transaction Level Modeling) models.
2. Virtual Queuing: Propagates transactions without modeling actual queues or delays but accurately reflects how traffic varies at each arbitration point. This method is used in TLM models, adding delay penalties in the transaction delay fields.
3. TLM Queuing: Incorporates transaction queues in high-level models of switching elements, requiring TLM blocking coding.
4. Cycle-Accurate Modeling: Simulates interconnects with clock cycle precision. This level of modeling can be applied at TLM or RTL (Register Transfer Level), capturing all events within each clock cycle.

Stochastic Interconnect Modeling

Network design extensively uses stochastic models, such as those based on Markov processes, to handle various types of random traffic. These models predict future states based solely on the current state and are effective with independent traffic sources and loads unaffected by round-trip delays. However, Markov models may not always resolve specific issues that arise in production chips, especially when traffic patterns are highly correlated, leading to inaccurate results.

Cycle-Accurate Interconnect Modeling

Cycle-accurate modeling is the most detailed form of interconnect modeling. It simulates individual traffic flows with clock cycle precision, which is particularly important when multiple traffic streams share the same NoC virtual channel. For example, when two packets arrive simultaneously at a switching element, arbitration causes delays, but if they arrive sequentially, those delays do not occur.

For full cycle-accurate interconnect modeling, each subsystem involved must operate at a cycle-accurate level. Inputs can come from trace data captured from real-world systems or artificially generated scenarios. In some cases, multiple clocks or precise modeling of clock edges may be required, and cycle-accurate models alone may not capture all necessary details.

Summary of Interconnect Modeling

Interconnect modeling is essential in SoC design, optimizing performance in the early design stages and addressing issues that may arise during production. Models can range from high-level static analysis to cycle-accurate simulations, each chosen based on specific design goals and requirements.

Comparison of NoC and Circuit-Switched Interconnects

Packetised Networks on Chip (NoC)

• Features:
  • Packet-Based Data Transmission: Data is divided into packets with metadata, such as destination addresses, and independently routed through the network.
  • Dynamic Routing: Packets are dynamically routed through network routers, selecting paths based on network conditions.
  • Flexible Architecture: Supports various topologies (e.g., mesh, ring, tree) to meet system requirements, offering high design flexibility.
  • Scalability: Easily scales with network size, functioning efficiently even in complex SoCs.
• Advantages:
  • High Flexibility: Supports various topologies and reduces congestion through dynamic routing.
  • Scalability: Easily accommodates large and complex SoC designs.
  • Minimized Bottlenecks: Multiple routing paths help reduce congestion.
  • Reusability: Modular design allows reuse of existing NoC infrastructure in new designs.
• Disadvantages:
  • Complex Routing and Control: Dynamic routing and packet switching increase router design complexity, potentially raising power consumption and design time.
  • Variable Latency: Different routing paths can lead to variable latency, problematic for real-time applications.
  • Power Consumption: Multiple routers and switches can increase power consumption.

Circuit-Switched Interconnect

• Features:
  • Circuit-Based Data Transmission: Establishes a dedicated path between nodes for data transmission, maintained until the transfer completes.
  • Fixed Path: The transmission path remains fixed during data transfer, with no path changes.
  • Simpler Control: Fixed paths simplify routing control.
• Advantages:
  • Consistent Latency: Fixed paths provide consistent latency, crucial for real-time applications.
  • Lower Power Consumption: Simpler routers and switches lead to lower power consumption, especially with optimized data paths.
  • Simpler Implementation: Fixed routing and control simplify implementation.
• Disadvantages:
  • Inefficient Resource Usage: Once a circuit is established, the path remains dedicated and unavailable to other traffic until data transfer ends, leading to inefficient resource usage.
  • Scalability Issues: As the network grows, the resources needed to set up and maintain circuits increase, limiting scalability for large SoCs.
  • Lack of Flexibility: Fixed paths mean no alternative routes during congestion, leading to potential bottlenecks.

Summary

• NoC: Offers superior flexibility and scalability but comes with challenges in routing complexity, power consumption, and variable latency.
• Circuit-Switched Interconnect: Provides consistent latency and lower power consumption but suffers from inefficient resource usage, limited scalability, and inflexibility.
• Choosing the Right Approach: The choice between NoC and Circuit-Switched interconnects depends on specific design goals and requirements, with each approach offering distinct strengths and trade-offs.

The Need for Cycle-Accurate Modeling

Cycle-accurate modeling means all subsystems in the SoC operate with precise clock cycle timing. To model the entire interconnect at a cycle-accurate level, every subsystem interacting with the interconnect must also be cycle-accurate.

Key Considerations

1. Accurate Timing Analysis: Cycle-accurate modeling captures every event at each clock cycle, ensuring that all interactions between subsystems exchanging data with the interconnect are precisely synchronized.
2. Performance and Latency Analysis: To accurately analyze overall SoC performance and latency, every subsystem must maintain the same level of timing accuracy. Cycle-accurate modeling detects changes at each clock cycle, providing a true evaluation of system performance.
3. Detailed Interaction Capture: Critical interactions between subsystems, such as data transfers and arbitration events, are accurately reflected only in cycle-accurate models. This level of detail is essential for complex SoCs, where minor timing errors can significantly impact overall system behavior.

Challenges and Practical Considerations

However, modeling an entire SoC at the cycle-accurate level is highly complex, time-consuming, and resource-intensive. For this reason, early design stages often rely on high-level modeling or TLM, applying cycle-accurate modeling selectively to critical components.

Summary

• To model an interconnect cycle-accurately, all connected subsystems must also be cycle-accurate.
• This level of modeling is crucial for precise performance and latency evaluations of the system.
• Due to the complexity and resource demands of cycle-accurate modeling, it is often reserved for critical areas, while higher-level modeling techniques are used elsewhere.
• Whether full SoC cycle-accurate modeling is necessary depends on the design goals and the specific needs of the analysis.

Korean Version: https://zeah.tistory.com/96