SystemC / TLM 2.0 Modeling
Loosely-timed and approximately-timed transaction-level models of processors, peripherals, and interconnects — fully compliant with the TLM 2.0 standard and ready for virtual platforms.
// San Jose, CA · SystemC · C++ · RTL Modeling
SystemC and C++ models of the blocks you can't afford to get wrong — and the behaviors the architecture spec leaves ambiguous. Written and reviewed by engineers who have debugged real silicon.
// About
Most blocks are well-behaved — standardized protocols, known patterns. Anyone can model those in a week.
The hard blocks are where the spec runs out: cross-domain interactions, sequencing the manual covers in one ambiguous paragraph, behavior that only shows up during bring-up. You don't learn that from a manual — you learn it from shipping silicon.
Before KO2U was a company, it was a habit. A laser held steady on a spinning disc by a control loop that was modeled before it was built. Hearts read through a patch on the chest. A camera that watches all day on nearly no power. Multiprocessors walked through, cycle by cycle, before a single transistor was drawn. Every system built twice — once in math, once in silicon. The math first. The silicon confirmed it.
That's what KO2U brings: SystemC and C++ models built by engineers who have sat through bring-up, stared at waveforms at 2 AM, and found the corner cases the spec never mentioned.
#include <systemc.h>
SC_MODULE(CpuModel) {
sc_in<bool> clk;
tlm_utils::simple_initiator_socket<CpuModel> socket;
void execute() {
// issue a TLM transaction
trans.set_address(0x4000_0000);
socket->b_transport(trans, delay);
}
SC_CTOR(CpuModel) {
SC_METHOD(execute);
sensitive << clk.pos();
}
};// Services
Loosely-timed and approximately-timed transaction-level models of processors, peripherals, and interconnects — fully compliant with the TLM 2.0 standard and ready for virtual platforms.
Cycle-accurate and cycle-approximate behavioral models written in modern C++, engineered for performance without sacrificing architectural fidelity.
Full-system virtual platforms that boot operating systems and run production firmware — enabling software teams to start long before first silicon.
Seamless integration with UVM environments, SystemVerilog DPI, and existing ESL flows. Co-simulation bridges between abstract models and RTL.
Instrumented models with profiling, tracing, and power estimation hooks — giving architects quantitative data for design decisions.
Custom checkers, monitors, and testbench components built on top of our models to catch bugs at the speed of abstraction.
Cut regression time from days to hours. The tools are free — knowing what's safe to accelerate isn't. That judgment is the job.
// Expertise
Anyone can name forty tools. The work only lives in a few.
Everything else — UVM, SystemVerilog DPI, QEMU — is integration, not identity.
// The blocks themselves
And the buses — AXI, AHB, APB? Anyone can model a bus.
// Where the silicon ships
// AI
We use AI every day — for scaffolding, for boilerplate, for reading unfamiliar legacy code. So does everyone else. The tool stopped being a differentiator the day it became free.
What AI can't do is decide. It writes confident code for the blocks that come with a manual — and the blocks we model are the ones the manual never covered. It has never sat through bring-up. It has never stared at waveforms at 2 AM. It doesn't know which corner cases are real.
So every line AI writes here meets the same bar as everything else we ship — reviewed by an engineer who has debugged silicon, correlated against RTL, quantitatively. AI takes none of the responsibility. We take all of it.
// AI-assisted model — header log
// ────────────────────────────
// generated by: ai
// corner cases: human
// correlated: vs RTL, quantitatively
// responsibility: ours// Process
We study your architecture specs and define the right abstraction level — accuracy vs. speed is a business decision, not a guess.
Iterative development with weekly drops. You get working code from week one, not a big-bang delivery at the end.
We validate model behavior against RTL simulation results and document accuracy with quantitative correlation reports. And when the two disagree — sometimes it's the RTL that's wrong. We've found client bugs this way.
Clean documentation, regression-tested delivery, and knowledge transfer so your team owns the models with confidence.
// Contact
Tell us which block keeps your team up at night. We'll tell you honestly whether modeling helps — and if it does, how accurately.
contact@ko2u.com