SystemC / TLM 2.0 Modeling
Loosely-timed and approximately-timed transaction-level models of processors, peripherals, and interconnects — fully compliant with the TLM 2.0 standard and ready for virtual platforms.
// San Jose, CA · SystemC · C++ · RTL Modeling
SystemC and C++ models of the blocks you can't afford to get wrong — MMUs, interconnects, and everything the architecture spec leaves ambiguous. Written and reviewed by engineers who have debugged real silicon.
// About
NoC interconnects are well-behaved — the protocols are standardized, the patterns are known. We model those too.
But MMUs are different. Page table walks that stall mid-flight. TLB shootdowns racing each other. Fault ordering that the architecture manual describes in one ambiguous paragraph. You don't learn that from a manual — you learn it from debugging real silicon.
That's what KO2U brings: SystemC and C++ models built by engineers who have sat through bring-up, stared at waveforms at 2 AM, and found the corner cases the spec never mentioned.
#include <systemc.h>
SC_MODULE(CpuModel) {
sc_in<bool> clk;
tlm_utils::simple_initiator_socket<CpuModel> socket;
void execute() {
// issue a TLM transaction
trans.set_address(0x4000_0000);
socket->b_transport(trans, delay);
}
SC_CTOR(CpuModel) {
SC_METHOD(execute);
sensitive << clk.pos();
}
};// Services
Loosely-timed and approximately-timed transaction-level models of processors, peripherals, and interconnects — fully compliant with the TLM 2.0 standard and ready for virtual platforms.
Cycle-accurate and cycle-approximate behavioral models written in modern C++, engineered for performance without sacrificing architectural fidelity.
Full-system virtual platforms that boot operating systems and run production firmware — enabling software teams to start long before first silicon.
Seamless integration with UVM environments, SystemVerilog DPI, and existing ESL flows. Co-simulation bridges between abstract models and RTL.
Instrumented models with profiling, tracing, and power estimation hooks — giving architects quantitative data for design decisions.
Custom checkers, monitors, and testbench components built on top of our models to catch bugs at the speed of abstraction.
Cut regression time from days to hours. We know exactly where 2-state simulation is safe — and where don't-cares will burn you. We port only what's safe.
// Expertise
// Process
We study your architecture specs and define the right abstraction level — accuracy vs. speed is a business decision, not a guess.
Iterative development with weekly drops. You get working code from week one, not a big-bang delivery at the end.
We validate model behavior against RTL simulation results and document accuracy with quantitative correlation reports. And when the two disagree — sometimes it's the RTL that's wrong. We've found client bugs this way.
Clean documentation, regression-tested delivery, and knowledge transfer so your team owns the models with confidence.
// Contact
Tell us which block keeps your team up at night. We'll tell you honestly whether modeling helps — and if it does, how accurately.
contact@ko2u.com